Quatech PCMCIA Card Register Programming

As with many Quatech serial port adapters, the Scratch Register (SCR) at base address + 7 has been overwritten with an Interrupt Status Register (ISR) or a Quatech Options Register (QOR), depending on whether or not the Divisor Latch Access Bit (DLAB) in the Line Control Register (LCR) has been set.

When DLAB is cleared, base + 7 is the ISR.  Because both ports share an interrupt, it can be useful for the driver to check to see which port is generating the interrupt.  Bit zero represents the first port, and bit one represents the second port.  This is a read-only register.

When DLAB is set, base + 7 becomes the QOR.  The two least significant bits are called the rate bits.  They affect the UART clock as follows:

00	X1 (1.8432 MHz)
01	X2 (3.6864 MHz)
10	X4 (7.3728 MHz)
11	X8 (14.7456 MHz)

Both ports must use the same clock rate multiplier.

Bit 4 of the QOR has been dubbed the Quatech Latch Access Bit (QLAB), and it controls access to the extended registers.  In order to set QLAB, the LCR must first be set to 0xBF.  Once QLAB is set, the Quatech Modem Control Register (QMCR) at base + 4 is exposed.  Its map is as follows:

D5		D4		D3		D2		D1		D0
Receiver Enable Mode:		Loopback Mode:		AUXIN Mode:		AUXOUT Mode:		Transmitter Enable Mode:
0=	Always on	0=	Use bits 2 & 3	0=	AUXIN Þ CTS TCLK Þ RCLK	0=	RTS Þ AUXOUT	00=	Always on
								01=	Toggle on DTR
1=	Opposite of TXEN	1=	TCLK Þ RCLK AUXIN Þ AUXOUT RTS Þ CTS	1=	AUXIN Þ RCLK RTS Þ CTS	1=	TCLK Þ AUXOUT	10=	Toggle on RTS
								11=	Auto-Toggle

All other bits are reserved and should always be zero whenever they are written to.